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https://archive.ph/TNLUr

A homelab box that never sleeps runs 8,760 hours a year. So the spec that decides what it costs you is not the one on the box. It is the one nobody prints: how many watts it pulls sitting at the login prompt doing nothing. I kept hitting this while shopping for a Proxmox node, so I put the measured numbers in one place. More on that at the end. First, why the spec sheet lies to you. TDP is a thermal budget, not a power reading TDP is the heat the cooler has to handle at full tilt. It is a design target for the heatsink, not a measurement of what the chip draws, and it says almost nothing about idle. Your homelab box spends 95%+ of its life idle, so the number that runs up the meter is idle wall power, and that number is never on the product page. The arithmetic is unforgiving. One watt running continuously is 8.76 kWh a year. So the gap between a 7 W box and a 35 W box is not 28 watts, it is about 245 kWh a year, every year, for as long as the box is on. Plug in your own rate to get the dollars; the point is the gap compounds. Where TDP actively misleads you A few measured results from the dataset I'll link below, all from third-party wall-meter readings, not vendor claims: The new N100 wave is genuinely low. A Minisforum UN100C measures 5 to 7 W at idle. Beelink, GMKtec and Trigkey N100 boxes land in the 6 to 10 W range. For a Pi-hole, a few containers and some light VMs, this tier is hard to beat on running cost. AMD mini PCs idle far higher than their marketing suggests. A Minisforum UM790 Pro measures 25 to 45 W at idle. A Beelink SER6 Pro lands at 20 to 35 W. These are fast little machines, but if you picked one expecting "small box, small draw," the meter disagrees, and over a year that delta is real money. Newer and higher-TDP is not lower-idle. A Dell OptiPlex 7060 Micro idles just over 18 W on its 65 W-TDP desktop chip. The older 7070 with a six-core part sits around 13 W, and the low-power "T" SKUs lower still. The CPU's TDP class predicted idle better tha

ᓯᐅᓇᕐᑕᖅ — Inuktitut for "that which lies ahead; a purpose" 🗣️ On the Name Full disclosure: I named this repository at 2 AM, which is probably when most repository names are decided. Siunertaq comes from Kalaallisut (West Greenlandic), a polysynthetic language — the kind where a single word can encode an entire clause's worth of meaning through agglutination and incorporation. I'm a bit of a grammar nerd, and polysynthetic languages have always fascinated me precisely because of how much structure they pack into a single morphological unit. One word carries subject, object, tense, evidentiality, and mood all at once, with none of it ambiguous if you know the grammar. That felt like the right metaphor for what this project is trying to do: pack a build graph's topology, its norm constraints, and its effect ordering into a single type-checkable unit — where the structure does the work, not the runtime. The word itself means something like "that which lies ahead; a purpose" — which seemed fitting for a tool that reasons about what needs to happen before anything actually runs. 🧵 TL;DR What if your task orchestration system couldn't even represent an ill-ordered build? Not "it would fail at runtime" — but "the type system refuses to construct the value in the first place." That's the idea behind Siunertaq : a Scala 3 project that combines Dhall (a total, non-Turing-complete configuration language), Cats Effect (purely functional async runtime), and a BSD Quiver model (directed Banach space graph) to make inconsistent build topologies structurally non-representable . This post walks through the design — with analogies aimed squarely at the Typelevel community — and closes with some thoughts on what modern AI-assisted development actually looks like when you refuse to let the LLM take the easy path. 🤔 Why Yet Another Build/Orchestration Abstraction? Most task orchestrators model their dependency graph as a mutable Map[Task, List[Task]] or similar at runtime, then check for