标签：#Hardware

Linux 7.1 Boosts Intel Arc, Flatpak Integrates ROCm, Vintage AMD Driver Refined Today's Highlights Recent developments enhance GPU performance and accessibility, with the Linux 7.1 kernel providing significant gains for Intel Arc Battlemage graphics. AMD's ROCm compute platform gains broader deployment potential through Flatpak 1.18 integration, while an older AMD GPU driver sees notable code cleanups. Linux 7.1 Helping Intel Arc Battlemage Graphics Achieve Better Performance (Phoronix) Source: https://www.phoronix.com/review/intel-b580-linux-71 Phoronix reports that the upcoming Linux 7.1 kernel release is delivering superior graphics performance for Intel's Arc B580 Battlemage desktop graphics card compared to the current stable Linux 7.0. This indicates ongoing, critical optimization work within the open-source Linux graphics stack, directly impacting the gaming and compute capabilities of Intel's latest GPU architecture. Such kernel-level improvements are vital for unlocking the full potential of new hardware on Linux platforms, ensuring users receive the best possible experience from their Intel Arc GPUs. The performance uplift suggests that deeper integration and fine-tuning of the kernel's display and compute drivers are progressing, addressing potential bottlenecks and enhancing throughput. For users and developers leveraging Intel Arc GPUs on Linux, this kernel update is a significant milestone, promising more stable and efficient operation for various workloads, from gaming to professional applications. It highlights the dynamic nature of Linux driver development, where continuous collaboration leads to tangible performance benefits even before major hardware refreshes. Comment: This shows how crucial kernel updates are for modern GPUs on Linux. Early adopters of Arc Battlemage should definitely keep an eye on Linux 7.1 for a noticeable performance bump. Flatpak 1.18 Released With Integration For AMD ROCm (Phoronix) Source: https://www.phoronix.com/news/Fl

Ask almost any engineer what "Wi-Fi" stands for and you'll hear the same answer: "Wireless Fidelity." It is one of the most repeated facts in tech, it appears in textbooks and product manuals, and it is wrong. Wi-Fi does not stand for Wireless Fidelity. In fact, it does not stand for anything at all. A name invented by a branding agency In 1999, the industry group then known as the Wireless Ethernet Compatibility Alliance — today the Wi-Fi Alliance — had a problem. The wireless networking standard it was promoting carried the memorable name "IEEE 802.11b Direct Sequence." That string is precise, but no consumer was ever going to ask a store clerk for an 802.11b router. The technology needed a brand. So the alliance hired Interbrand, the same firm behind names like Prozac and the Compaq brand, to invent something catchy. Interbrand returned with a shortlist of about ten candidates, and the group chose "Wi-Fi." Phil Belanger, a founding member of the alliance, has been blunt about it for years: the name has no expanded meaning. It was picked because it was short, easy to say, and rhymed with "Hi-Fi," a term consumers already associated with high-quality audio gear. So where did "Wireless Fidelity" come from? The myth has a real origin. Some board members were uncomfortable shipping a brand name that "meant nothing," so the alliance briefly bolted on the tagline "The Standard for Wireless Fidelity." It was a backronym — two words reverse-engineered to fit the syllables "Wi" and "Fi" after the fact. The phrase was clumsy, it never described the technology accurately, and once the alliance brought on more marketing-savvy members it was quietly dropped. The tagline disappeared; the misconception it planted did not. Why this matters if you build connected things This is a fun piece of trivia, but it points at something real for anyone doing IoT and embedded development . The protocols we treat as immovable technical bedrock are often shaped as much by branding, licensing,

Apple's WWDC nears: Here's what you can look forward to.

The first time I encountered an EIA-96 resistor , I assumed the marking would tell me the resistance value directly. I was troubleshooting a PCB and found a resistor marked 24C . Naturally, I expected some relationship between "24" and the actual resistance. After measuring and checking the datasheet, I discovered the resistor was 17.4 kΩ . That raised an obvious question: Why doesn't the code match the resistance value? The Problem With Traditional SMD Codes Most electronics enthusiasts learn resistor markings through familiar examples: 103 = 10 kΩ 472 = 4.7 kΩ 681 = 680 Ω These markings are straightforward. The first digits are significant figures and the last digit is a multiplier. The system works well for common resistor values, especially 5% tolerance components. However, things become complicated when manufacturers need to identify large numbers of precision resistor values on extremely small packages. Enter the EIA-96 Series Precision resistors often use the E96 preferred value series. Instead of having only a handful of values per decade, the E96 series contains 96 standardized resistance values between powers of ten. Some examples include: 100 Ω 102 Ω 105 Ω 107 Ω 110 Ω 113 Ω Notice how closely spaced these values are. Trying to represent all of them with traditional three-digit markings would quickly become messy and inconsistent. A Different Approach Rather than printing the resistance value directly, EIA-96 uses an index system. Each number from 01 to 96 corresponds to one of the standard E96 values. For example: Code Base Value 01 100 24 174 68 499 96 976 A letter is then added to indicate the multiplier. So the resistor marking becomes: Number + Letter Instead of: Resistance Value Example: Decoding 24C Let's break down 24C. First, look up the base value: 24 → 174 Next, decode the multiplier letter: C → ×100 Now calculate: 174 × 100 = 17,400 Ω Final resistance: 17.4 kΩ At first glance, nothing about "24C" resembles 17.4 kΩ, but that's because the code i

Ask a roomful of engineers where the name "Arduino" comes from and you will get confident answers about acronyms, Italian for "bold friend," or some clever electronics pun. Almost all of them are wrong. The most influential open-source microcontroller board in history — the one that introduced millions of students, artists, and tinkerers to embedded development — is named after a bar. The pub in Ivrea The story begins in Ivrea, a small town in northern Italy straddling the Dora Baltea river. In the early 2000s it was home to the Interaction Design Institute Ivrea, where a team led by Massimo Banzi was looking for a cheap, approachable way to teach design students how to make things that sense and respond to the world. The tools available at the time were either too expensive or too intimidating for people who were not electrical engineers. So, in 2005, the team built their own board and released the design as open hardware. They needed a name. Banzi and his collaborators were regulars at a local pub called Bar di Re Arduino — "the Bar of King Arduino." When it came time to christen the project, the bar's name stuck. There was no acronym, no marketing committee, no focus group. The board was named after the place where the people who made it spent their evenings talking through ideas. The medieval king behind the bar The bar itself carries a much older name. Arduin of Ivrea — Arduino in Italian — was a real historical figure, an Italian nobleman who became King of Italy in 1002 and held the crown until 1014. He is one of Ivrea's famous "underdog kings," remembered locally long after his short reign ended. So the chain runs a thousand years deep: a development board used in connected sensors and robots today is named after a pub, which was named after an early-medieval king who ruled around the year 1000. It is the kind of detail that sounds like trivia, but it points at something real about how durable technology actually comes together. Why the origin story matters

Apple's WWDC nears: Here's what you can look forward to.

While the AI fundraising machine keeps breaking its own records, some founders are building in the other direction. Mirror founder Brynn Putnam just raised money for Board, a startup focused on bringing people together through in-person games and social experiences. Cyberdeck creators are going viral crafting whimsical DIY computers that literally encourage users to touch grass. Unlike the AI-free browser crowd, this doesn’t just feel like backlash, […]

Apple's WWDC nears: Here's what you can look forward to.

The Ring 5, which Oura describes as the world’s smallest smart ring, is 40% smaller than its predecessor and starts at $399.

这视频由知名半导体分析机构 SemiAnalysis 发布，围绕 AI 数据中心网络演进中铜（Copper）与板载共封装光学（CPO - Co-Packaged Optics）的竞争和未来进行了极其硬核且详细的深度拆解。 视频的核心逻辑可分为以下几个关键板块： 一、 背景：铜的物理极限与三大网络层级 1. 铜的物理极限 视频开篇强调，半导体一直依赖铜（如芯片金属层、主板走线、NVL72机架的背板总线）。但当单通道传输速率达到 200 Gbits/second (每路) 及以上时，铜的传输距离极限被死死卡在 2米以内 [ 00:55 ]。超过这个距离，现代 AI 服务器的庞大带宽需求就只能依赖光纤和激光 [ 01:01 ]。 2. AI 数据中心的三大网络层级 [ 01:43 ] 前端网络（Front-end Network）： 负责基础的数据加载、SSH 访问和用户请求，带宽要求最低 [ 01:51 ]。 纵向扩展网络（Scale-up Network）： 连接单机架内的所有计算和网络托盘（如英伟达的 NVLink），让多张 GPU 能以极高带宽、极低延迟像“单张 GPU”一样协同工作 [ 02:07 ]。其带宽需求是 Scale-out 的 10 倍 [ 03:47 ]。 横向扩展网络（Scale-out Network）： 负责机架与机架之间、甚至整个数据中心范围内的服务器互联 [ 03:00 ]。其带宽需求是前端网络的 8 到 10 倍 [ 03:47 ]。 二、 传统可插拔光模块（Pluggable Transceivers）的致命痛点 在需要跨机架的 Scale-out 网络中，目前行业标配是可插拔光模块（如 OSFP、QSFP-DD） [ 04:29 ]。 视频拆解了它的四大组成部分： 物理接口、DSP（数字信号处理器）、TOSA（激光发射组件）、ROSA（光接收组件） [ 05:03 ]。 视频提出了一个颠覆直觉的事实： 耗电和延迟的元凶根本不是激光器（仅占15%功耗），而是 DSP。 [ 06:06 ] 功耗： DSP 消耗了光模块高达 60% 以上 的电能 [ 06:21 ]。 延迟： 信号从电转换到光通常会带来 150 到 200 纳秒的延迟，其中 90% 以上由 DSP 造成 [ 06:28 ]。 为什么必须要 DSP？ 因为 GPU 或交换机生成的电信号，在穿过芯片封装、主板走线到达机架边缘的光模块（约 30 厘米距离）时，信号已经严重衰减和失真，必须通过 DSP 进行放大和“清洗” [ 07:17 ]。而 CPO 的核心存在意义，就是将光学引擎无限靠近源头，彻底消灭 DSP [ 06:57 ]。 三、 从 LPO 到 CPO 的技术演进路径 为了干掉 DSP，行业尝试了多种方案： LPO（线性可插拔光模块）： 做法很大胆，直接拿掉可插拔模块里的 DSP，强行把失真的电信号转成光信号发出去。虽然有用，但极大牺牲了传输距离 [ 08:25 ]。 OBO（板载光学）： 把光模块从机架边缘移到主板上更靠近芯片的位置。但由于距离还不够近，没能彻底干掉 DSP，同时还丢掉了可插拔的便利性，宣告失败 [ 09:06 ]。 NPO（近封装光学）： 将光学引擎移至与 ASIC（交换机芯片/GPU）极近的特殊高特性基板上，是目前正在落地的折中方案 [ 09:38 ]。 CPO（共封装光学）： 终极形态，将光学引擎与芯片直接封装在同一个 Package 上 [ 10:01 ]。 视频中拆解的 CPO 三大阶梯（Tiers）： 第一阶梯（最低限度）： 光学引擎与交换机芯片在同一封装基板上，通过铜走线连接。虽干掉了 DSP，但仍需要 SerDes 进行并行/串行信号转换 [ 10:31 ]。 第二阶梯（中介层集成）： 芯片与光学引擎坐落在同一个硅基或有机中介层（Interposer）上，互连密度大幅提升， 彻底不再需要 SerDes ，实现完全的并行集成 [ 11:01 ]。 终极 Boss 级： 利用混合键合（Hybrid Bonding）等 3D 堆叠技术（2.5D 如台积电的 COW-AMH），将光学引擎直接叠在芯片上方或下方，实现极致的低功耗 [ 11:31 ]。 四、 CPO 的商业落地博弈：Scale-out 网络 CPO 的首个落地目标是替代 Scale-out 网络中的传统光模块 [ 12:46 ]。然而，行业对此产生了严重分歧： 传统可插拔的优势： 坏了极易更换（运维成本低）；标准统一、供应商极多，大厂拥有极强的 价格控制权 且能避免 供应商锁定（Vendor Lock-in） [ 13:29 ]。 CPO 的软肋： 它是封装级别的。如果你买英伟达或博通的 CPO 芯片，你就必须绑定购买他们的整套光学方案；一

Meta appears to have listened to the Supernatural users who protested the app's sad fate after sweeping layoffs.

The breach at wearable ring maker Ultrahuman stemmed from credentials stolen from a malware-infected employee laptop.

Over the last few months, these DIY hardware communities have exploded in popularity as people on social media show off their solar-powered game emulators, pocket-sized ereaders, and clamshell purse computers.

Board, the startup building what it calls "together tech" designed to bring people into the same room, has closed a Series A led by Union Square Ventures.

The women building these over-the-top, bedazzled cyberdecks aren’t in it for the glitter alone. This trend is reaching its peak at a time when people feel powerless against big tech.

The MacBook Neo shipped 1.1 million units in its first weeks on sale, IDC estimates, as Apple pushes deeper into the mainstream laptop market.

A homelab box that never sleeps runs 8,760 hours a year. So the spec that decides what it costs you is not the one on the box. It is the one nobody prints: how many watts it pulls sitting at the login prompt doing nothing. I kept hitting this while shopping for a Proxmox node, so I put the measured numbers in one place. More on that at the end. First, why the spec sheet lies to you. TDP is a thermal budget, not a power reading TDP is the heat the cooler has to handle at full tilt. It is a design target for the heatsink, not a measurement of what the chip draws, and it says almost nothing about idle. Your homelab box spends 95%+ of its life idle, so the number that runs up the meter is idle wall power, and that number is never on the product page. The arithmetic is unforgiving. One watt running continuously is 8.76 kWh a year. So the gap between a 7 W box and a 35 W box is not 28 watts, it is about 245 kWh a year, every year, for as long as the box is on. Plug in your own rate to get the dollars; the point is the gap compounds. Where TDP actively misleads you A few measured results from the dataset I'll link below, all from third-party wall-meter readings, not vendor claims: The new N100 wave is genuinely low. A Minisforum UN100C measures 5 to 7 W at idle. Beelink, GMKtec and Trigkey N100 boxes land in the 6 to 10 W range. For a Pi-hole, a few containers and some light VMs, this tier is hard to beat on running cost. AMD mini PCs idle far higher than their marketing suggests. A Minisforum UM790 Pro measures 25 to 45 W at idle. A Beelink SER6 Pro lands at 20 to 35 W. These are fast little machines, but if you picked one expecting "small box, small draw," the meter disagrees, and over a year that delta is real money. Newer and higher-TDP is not lower-idle. A Dell OptiPlex 7060 Micro idles just over 18 W on its 65 W-TDP desktop chip. The older 7070 with a six-core part sits around 13 W, and the low-power "T" SKUs lower still. The CPU's TDP class predicted idle better tha

If Nvidia has cracked a way to bring AI agents easily, safely and usefully to the masses, it could — and should — be big.

Intel Foundry's Rio Rancho Facility Moves Toward Glass Substrate Volume Production Reports from Wccftech and Forbes (May 26, 2026) indicate that Intel Foundry's facility in Rio Rancho, New Mexico, is advancing toward becoming the world's first factory to achieve mass production of glass substrates — a next-generation chip packaging technology considered critical for scaling AI hardware beyond current organic substrate limitations. The facility has already begun manufacturing silicon photonics products for external customers and is expected to play a central role in Intel's advanced packaging strategy. Why Glass Substrates Matter for AI Glass substrates address fundamental limitations of current organic (ABF) substrates that are becoming bottlenecks for AI chip scaling: Extreme flatness (<1 μm warpage) enables larger die and chiplet assemblies Low CTE (3-8 ppm/°C) closely matches silicon (2.6 ppm/°C), reducing thermal stress Higher interconnect density due to dimensional stability Better high-frequency performance with low dielectric loss Larger format supporting bigger interposers than organic substrates For AI accelerators that already push CoWoS substrate limits at 5,500+ mm², glass substrates could enable even larger multi-chiplet assemblies. Intel's Advanced Packaging Ecosystem Intel has been building an advanced packaging portfolio: EMIB (Embedded Multi-die Interconnect Bridge): High-density die-to-die connections Foveros : 3D stacking for logic-on-logic packaging Co-Packaged Optics (CPO) : Recently demonstrated glass-core substrate prototypes with CPO Customer Base According to Forbes: Existing customers : AWS, Cisco Reportedly in discussion : Apple, Google, Microsoft, Nvidia, Tesla Commercial Timeline Milestone Timeline Glass substrate R&D announcement 2023 Pilot line (Chandler, AZ) 2024-2025 Silicon photonics production (Rio Rancho) 2026 (active) Glass substrate volume production ~2028-2030 Global Competition Intensifying SKC/Absolics (Korea): Operating pilo

Meta seems to be making big bets on AI-powered hardware.