Crypto-Agility Without a Redesign: The "Soft-Fade-Out" Pattern for Legacy IoT Silicon

Most conversations about CRA, DORA, and NIS2 compliance for IoT hardware boil down to one uncomfortable binary: redesign the board around newer, security-capable silicon, or accept that your existing product line falls out of compliance on a fixed deadline. For a product with years left in its lifecycle and a BOM that took months to qualify, "just redesign it" is rarely a real answer. There's a third option that gets far less attention than it deserves: pair the legacy chip with a modern security co-chip that absorbs the cryptographic boundary, while the legacy part keeps doing exactly what it already does well - application logic, peripherals, display, sensor polling. Call it a soft fade-out. The old silicon stays in service until its natural end-of-life; the compliance gap gets closed by a second, much cheaper part sitting next to it, not by replacing it. The Three Gaps a Legacy Chip Has - and Why a Co-Chip Fixes Them The regulatory pressure driving all of this isn't abstract. NIST finalized its post-quantum cryptography standards in 2024, and IR 8547 sets real dates: ECDSA and RSA are deprecated after 2030, disallowed after 2035. Germany's BSI has gone further - TR-02102-1 (2026 edition) sets a stricter 2030 deadline for high-protection-need data, and treats the migration as "alternativlos" (without alternative) rather than a recommendation. Older embedded silicon typically lacks three things simultaneously: a hardware-isolated key store (TEE/APM), side-channel countermeasures (DPA protection) strong enough for physical-access threat models, and enough RAM/compute headroom to run lattice-based PQC algorithms in software without starving the rest of the firmware. Redesigning the whole board to fix all three at once is expensive and slow. But none of those three gaps require touching the part that's already doing its job - they're all boundary problems. A second, purpose-built chip can own the boundary. Three concrete pairings Using the ESP32 family as a worked exa